1. Field of the Invention
The present invention relates to an image processing apparatus and an image processing method, and a portable imaging apparatus using the same, such as a digital still camera, etc. More particularly, the present invention relates to an image processing apparatus and an image processing method in which image data is processed by repetition of data transfer between an image processing module which subjects local image data to a predetermined image processing, and a large-scale memory capable of storing data an entire image data, by means of direct memory access (hereinafter referred to as DMA) but not via a CPU, and to a portable imaging apparatus including the same.
2. Description of the Related Art
An exemplary digital still camera works in the following manner. Image data is captured by a charge coupled device (CCD) through a color filter. The captured image data is split and converted from RGB data on a Bayer array to YcbCr luminance data and color difference data which are then subjected to a JPEG compression process. The resultant image data is stored in a memory card or the like. Alternatively, the YcbCr luminance data and color difference data are subjected to data decompression processing or conversion to video signals, and the resultant data is displayed for monitoring an image before taking a picture. The data stored in the memory card is read out and displayed.
Such an apparatus for processing image data may comprises a CPU 101, a DMA controller 102, n image processing modules 103, a memory controller 104, an external memory 105, etc. as shown in FIG. 10, in which data is transferred via a data bus 106. In this apparatus, for example, digital data is obtained from a CCD, then the digital data is split and converted to luminance data and color difference data, those data are subjected to a JPEG compression process and a conversion process to video signals, and the like by the corresponding image processing modules 103. Only one image processing module 103 may be present in the apparatus.
In such image processing, a vast amount of data needs to be processed. In actual image data, data of a pixel is closely correlated to data of pixels around that pixel. The same processing is often repeatedly applied to data corresponding to a cluster of closely correlated pixels in a local region. Therefore, in order to efficiently process data of such a cluster of pixels in a local region, each image processing module 103 works as follows. Data is read from the external memory 105 in accordance with addresses regularly generated by the DMA controller 102 and then transferred to the image processing modules 103. Alternatively, data processed by the image processing modules 103 is similarly transferred to the external memory 105 by the DMA controller 102 and is stored in the external memory 105.
Data transfer between each image processing module 103 is conducted via the external memory 105. In this case, the DMA controller 102 appropriately manages transfer requests from each of the image processing modules 103 in accordance with priorities or the like thereof. One of the image processing module 103 which received an acknowledge signal from the DMA controller 102 uses the data bus 106 or the external memory 105. In this manner, the external memory 105 and the data bus 106 are shared by the image processing modules 103, thereby simplifying the whole structure of the image processing apparatus.
In such an image processing apparatus, when only a portion (shaded portion) of an entire image data stored in the external memory 105 is processed as shown in FIG. 11, the image data of horizontally-arranged pixels on continuous lines on a screen are not stored at continuous addresses in the external memory 105 as shown in FIG. 12 (shaded portion). FIG. 11 schematically shows the relationship between the positions of pixels on a screen and the address space of the external memory 105 storing data corresponding to the pixels. In FIG. 11, (PIXEL+1) pieces of data which are stored in a lateral (horizontal) line is processed. The (PIXEL+1) pieces of data are a part of data stored in one line in the external memory 105. In FIG. 12, pixel data corresponding to each horizontal line on the screen is stored in a portion (PIXEL+1) in the address space of the external memory 105 which corresponds to one line in the address space (corresponding to an address increment of INCPX).
In this case, pixel data is read from a two-dimensional array in the address space of the external memory 105 and is then transferred. Such processing is disclosed, for example, in Japanese Laid-Open Publication No. 63-98056.
The processing method described in the above-described publication will be described below with reference to FIG. 11. In FIG. 11, INCPX represents an address increment between two adjacent lines in the address space of the external memory 105; PIXEL+1 represents the width of a region of image data to be currently transferred; BASE represents the start address of the region from which data transfer begins; and END represents the end address of the region at which the data transfer ends. In one-time actuation of the DMA controller 102, such a rectangular region of image data required for image processing is read out and transferred to the image processing module 103.
In this case, the DMA controller 102 begins reading from the leftmost address BASE+0, and reads image data from the external memory 105 while successively pointing the addresses in a horizontal direction toward the right pixel by pixel (+1). The read-out data is transferred to the image processing module 103. After the address is BASE+PIXEL (the line width is PIXEL+1), the DMA controller 102 then points to a leftmost pixel positioned a line below, where the address of the pixel is BASE+INCPX. Similarly, the DMA controller 102 reads image data from the external memory 105 while successively pointing the addresses in the horizontal direction toward the right pixel by pixel (+1). The read-out data is transferred to the image processing module 103. In this manner, the address pointing, data reading and data transfer are continued until the address is eventually END. This process is one-time DMA actuation.
In addition, the start address, and the width and length of a region on a screen to be processed may be changed.
For the purposes of filtering for noise reduction, image enlargement using first-order interpolation, image reduction, etc., and compression and decompression, etc., data values are taken from a pixel to be processed and its surrounding pixels. The data values are multiplied by coefficients and are subjected to addition, subtraction, etc. In other words, a screen is divided into blocks. Data is read from a memory on a block-by-block basis, and is transferred to an image processing module. The image processing module processes data on a block-by-block basis, and the processed data is then transferred on a block-by-block basis to be stored in a memory.
In this case, the image processing module sometimes has to simultaneously access the image data of a plurality of pixels in a block. To this end, the image processing module needs to include a buffer (buffer memory) for temporarily storing the image data. The capacity of such a buffer influences the size of an LSI chip. Therefore, the buffer is preferably as small as possible.
When such block-by-block transfer is performed in one-time actuation of DMA transfer in accordance with the conventional technique described in the above-described Japanese Laid-Open Publication No. 63-98056, an address space region to be subjected to image processing is horizontally scanned from a leftmost pixel (e.g., corresponding to BASE+0) to a rightmost pixel (e.g., corresponding to BASE+PIXEL) so that all pixel data in a horizontal line is read out and transferred.
Therefore, the image processing module needs to include a buffer having at least a capacity of the vertical size of a block×the transfer line width (as indicated by the blank portion in FIG. 13) so as to store data from a region of the address space of the memory (to be processed) in which data to be transferred is stored as shown in FIG. 13. After stored into the buffer, the data is processed on a block-by-block basis.
For this reason, the buffer capacity has to be large. However, if the buffer capacity is limited, the maximum line width of an image region which can be processed is limited. The capacity of a buffer is actually designed to be two times or the like the size of a unit block by taking data holding into consideration. For the sake of simplicity, this is not explained.
Alternatively, if the size of data to be transferred is the vertical size of a block×the width of a block, the buffer capacity can be small. In this case, however, the DMA controller needs to be activated for every block transfer, adversely elongating a processing time required for processing an entire image.